The present invention relates to communication systems and integrated circuit (IC) devices. More particularly, the present invention provides for improved methods and devices for clock phase detection.
Over the last few decades, the use of communication networks exploded. In the early days Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small. Today, Internet and mobile applications demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files. For example, a social network like Facebook processes more than 500 TB of data daily. With such high demands on data and data transfer, existing data communication systems need to be improved to address these needs.
An important aspect of communication systems involves high-speed clock routing. High speed clock routing usually involves routing differential signals through several buffers before reaching a target destination, such as a flip-flop, mixer, or data converter. In many applications, precise control of the skew between positive and negative terminals of a differential clock is critical as it may introduce timing errors or reduce timing margins in the data path.
With control over skew being a necessity, phase detectors are an integral component of any feedback timing circuit, such as phase-locked loops (PLLs) or delay locked loops (DLLs). These detectors measure the phase difference between two input clocks, which in turn is used as a feedback signal to control the differential phase adjustment of the input clocks. Although there are several types of devices and methods related to clock phase detection, they have been inadequate for the advancement of various applications. Therefore, improved methods of clock phase detection are highly desired.